FREE COURSE / REAL PRACTICE
AArch64
Study AArch64 registers, AAPCS64 calling conventions, control flow, vector operations and memory ordering.
What you’ll work toward
Read and write small assembly routines and compare compiler output using the named cross-compilation and emulation tools.
Read an explanation, inspect the diagrams and work through the available checks, debugging exercises and builds. Feedback and prerequisite links guide the next step.
Before you start
This course builds on these skills:
Individual lessons can add prerequisites. The course map shows your actual readiness.
A look inside the first lesson
AArch64 registers, loads and constants
#include <cstdio>
extern "C" unsigned long write_w();
extern "C" long sign_ext(int x);
asm(R"(
.text
.globl write_w
write_w:
mov x0, -1 // all 64 bits set
mov w0, 7 // 32-bit write: upper half cleared
ret
.globl sign_ext
sign_ext:
sxtw x0, w0 // int -> long
ret
)");
int main() {
std::printf("%#lx\n", write_w()); // 0x7
std::printf("%ld\n", sign_ext(-5)); // -5
}Your course outline
Follow the lessons in curriculum order. Open a unit to preview the ideas you’ll work with.
AArch64: reading the machine
- LESSON 01.01
AArch64 registers, loads and constants
Read and write AArch64 data movement: x/w registers and the zero register, sized and sign-extending loads, the register-offset, pre- and post-index addressing modes, building 64-bit constants with movz/movk, and bitfield extracts.
Open lesson - LESSON 01.02
The AArch64 calling convention (AAPCS64)
Where AArch64 functions find their arguments and leave their results: x0–x7 and v0–v7, the x8 indirect result, callee-saved x19–x28 and d8–d15, frame records with fp and lr, 16-byte sp alignment, and how structs are passed (HFAs, ≤ 16 bytes in registers, larger by reference).
Open lesson - LESSON 01.03
AArch64 control flow: NZCV, b.cond, csel and ccmp
Read and write the instructions behind every if, loop and switch on AArch64: the NZCV flags, signed versus unsigned condition codes, cbz/tbz shortcuts, the conditional-select family (csel, cset, cinc, csneg), ccmp chains for && without branches, rotated loops and jump tables.
Open lesson - LESSON 01.04
Writing functions in AArch64 assembly
Write whole functions in AArch64 assembly (GAS): frame records with stp/ldp, saving callee-saved registers in pairs, post-index loops over arrays and strings, and calling back into C++ with blr while keeping sp 16-byte aligned.
Open lesson
AArch64: SIMD, ordering, codegen
- LESSON 02.01
NEON intrinsics
Program AArch64's Advanced SIMD unit directly: 32 registers of 128 bits in 16B/8H/4S/2D arrangements, compares that make all-ones masks, across-lane reductions, widening and narrowing, de-interleaving loads, and life without movemask.
Open lesson - LESSON 02.02
SVE: vector-length-agnostic SIMD
Write SIMD code that runs at any vector length from 128 to 2048 bits: svcnt*, while-predicates instead of scalar tails, merging vs zeroing predication, predicated loads, widening loads and reductions.
Open lesson - LESSON 02.03
The AArch64 memory model
What weakly ordered ARM hardware may reorder (almost everything), what ldar/stlr/ldapr and dmb buy you, how atomic read-modify-writes compile (LL/SC, LSE, outline atomics), and why code that works on x86 breaks here.
Open lesson - LESSON 02.04
AArch64 codegen, side by side with x86-64
The same C++ on both machines: fused multiply-add and conditional select, shifted operands, bitfield instructions, immediates that don't fit, conditional compare chains, load/store pairs — and how to write C++ that lands on the good idioms.
Open lesson